Formal Semantics and Proof Techniques for Optimizing VHDL Models(English, Paperback, Umamageswaran Kothanda)
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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
