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This Document Describes Valueram'S 256m X 64-Bit (2gb) Ddr3-1333 Cl9 Sdram (Synchronous Dram), 2rx8 Memory Module, Based On Sixteen 128m X 8-Bit Ddr3-1333 Fbga Components. The Spd Is Programmed To Jedec Standard Latency Ddr3-1333 Timing Of 9-9-9 At 1.5v. This 240-Pin Dimm Uses Gold Contact Fingers. Cl(Idd) 9 Cycles Row Cycle Time (Trcmin) 49.5ns (Min.) Refresh To Active/Refresh 110ns (Min.) Command Time (Trfcmin) Row Active Time (Trasmin) 36ns (Min.) Power (Operating) 1.800 W* Ul Rating 94 V - 0 Operating Temperature 0o C To 85o C Storage Temperature -55o C To +100o C - Jedec Standard 1.5v (1.425v 1.575v) Power Supply - Vddq = 1.5v (1.425v 1.575v) - 667mhz Fck For 1333mb/Sec/Pin - 8 Independent Internal Bank - Programmable Cas Latency: 9, 8, 7, 6 - Programmable Additive Latency: 0, Cl - 2, Or Cl - 1 Clock - Programmable Cas Write Latency(Cwl) = 7 (Ddr3-1333) - 8-Bit Pre-Fetch - Burst Length: 8 (Interleave Without Any Limit, Sequential With Starting Address "000" Only), 4 With Tccd = 4 Which Does Not Allow Seamless Read Or Write [Either On The Fly Using A12 Or Mrs] - Bi-Directional Differential Data Strobe - Internal(Self) Calibration: Internal Self Calibration Through Zq Pin (Rzq : 240 Ohm ± 1%) - On Die Termination Using Odt Pin - Average Refresh Period 7.8us At Lower Than Tcase 85degc, 3.9us At 85degc < Tcase < 95degc - Asynchronous Reset - Pcb: Height 0.740" (18.75mm), Double Sided Component