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UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly. UVM consists of a defined methodology for architecting modular testbenches for design verification. UVM has a library of classes that helps in designing and implementing modular testbench components and stimulus. This enables re-using testbench components and stimulus within and across projects, development of Verification IP, easier migration from simulation to emulation etc.