3 Review(s)

Features This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result,and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect the new focus on the design methodology. This book was written to help hardware design engineers learn how to write good VHDL design descriptions. The goal is to provide enough VHDL adn design methodology information to enable a designer to quickly write good VHDL designs and be abole to verify the results. It will also attempt to bring the designer with little or no knowledge of VHDL, to the level of writing complex VHDL descriptions. This book is organized into t hree logical sections. The first section of the book will introduce the VHDL language, the second section walks through a VHDL based design process including simulation, synthesis, place and route, and VITAL simulation; and the third section walks through a design examples of a small CPU design from VHDL capture to final gate-level implementation, and At-speed debugging.